1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns a device and a fabrication process, whereby a Magnetoresistive Random Access Memory (MRAM) structure can be formed.
2. Description of the Related Art
MRAM is a developing technology that offers the advantages of non-volatile memory with high-density fabrication. An MRAM structure employs the properties of layered magneto-resistive materials, which utilize the spin characteristics of electrons to produce a selective resistance differential across the MRAM structure. Changes in the spin characteristics of magneto-resistive materials result in changes in the resistance of the MRAM structure, and changes in resistance may be sensed thereby permitting the use of layered magneto-resistive materials in logic state devices.
MRAM devices typically include a pinned (spin stationary) layer, a soft (spin programmable) layer, and a non-magnetic layer interposed therebetween. The soft or sense layer may be programmed through the application of an external magnetic field and the net magnetization vectors between the programmable layer and the pinned layer may be changed between two discrete quantities, which may then be sensed to detect the programmed logic state of the MRAM device.
MRAM devices follow the same high-density fabrication techniques as their semiconductor counterparts. Integrated circuit (IC) fabrication techniques employ sequential steps of layered processing of materials. In one aspect, current manufacturing processes utilize a flow process that deposits a layered magnetic stack structure onto a substrate, where the deposition of the layered magnetic stack structure includes the deposition of the magnetic pinned layer, the non-magnetic layer, and the magnetic sense layer onto the substrate. Once the magnetic stack structure is deposited, the magnetic pinned layer is defined with a photo patterning and dry or wet etching process in a manner known in the art. The last step in the flow process planarizes the magnetic stack structure to define a plurality of magnetic bit shapes using a dry or wet etching process, and then a top electrode is added to complete the MRAM memory structure.
One disadvantage to utilizing a selective wet etching process and/or a dry etching process to define the magnetic bit shapes and/or the magnetic stack structure is that it leaves substantially rough edges, which may reduce the switching reliability of the MRAM device. In addition, another disadvantage is that utilizing a selective wet etching and/or a dry etching process may undercut the barrier layer, which undermines the integrity of the barrier layer and may cause electrical shorting of the magnetic sense layer and/or the magnetic pinned layer. The electrical shorting effect may also contribute to unreliable switching of the MRAM device due to an uncontrolled leakage current.
Still another disadvantage to a selective wet etching and/or a dry etching process is the generation of a non-uniform magnetic bit shape. A non-uniform magnetic bit shape may adversely effect the magnetic coupling and the resistance of the magnetic stack structure. Unfortunately, irregular shapes and non-uniform structures may produce unpredictable magnetic coupling patterns that may require a larger magnetic field for switching. An adverse increase in the magnetic coupling effect of the magnetic stack structure may require a larger magnetic field for switching, which may result in a larger current draw through the MRAM device. Additionally, increased resistance through the magnetic stack structure may also require a larger current draw through the MRAM device. As a result, an increase in the current consumption of the MRAM device reduces the power efficiency of the MRAM device, which is disadvantageous to low power requirements of some electronic devices, such as laptop computers and cellular phones.
Based on the foregoing, there currently exists a need for an improved magnetic memory device that comprises magnetic memory stack layers with improved magnetic coupling characteristics and stability. Furthermore, there also exists a need for a magnetic memory fabrication process that reduces the use of a selective wet etching process or a dry etching process to define the magnetic bit shapes and/or the magnetic stack structure in a manner so as to improve the switching reliability of the magnetic memory device.
The aforementioned needs are satisfied by the process flow for forming MRAM structures as described herein below. In one embodiment, the aforementioned needs may be satisfied by an MRAM cell comprising a substrate, a first electrode formed adjacent to the substrate, a pinned layer formed on the substrate so as to overlie the first electrode and be electrically coupled therewith, and an insulating layer formed on the pinned layer, wherein the insulating layer is formed so as to define a bit recess. In addition, the MRAM cell may further comprise a sense layer positioned in the bit recess such that regions of the sense layer at the outer perimeter of the bit recess produce a magnetic field that has a component directed away from the pinned layer, and a second electrode connected to the sense layer, wherein application of voltage differential between the first and the second electrode results in a change in the magnetic state of the sense layer thereby resulting in a detectable change in the resistance of the MRAM cell.
In one aspect, the substrate may be formed using a semiconductor based material, wherein the semiconductor based material includes a silicon wafer. The first electrode may be formed using a damascene process, wherein the first and second electrodes comprise a conductive material, such as copper. The pinned layer may produce a magnetic field with a component in a fixed direction. In addition, the pinned layer may comprise NiFe, the sense layer may comprise NiFeCo, and the insulating layer may comprise an insulating material selected from the group consisting of Silicon Dioxide, Tungsten, and Tantalum. Additionally, the bit recess may comprise sloped interior walls, wherein a barrier layer may be formed so as to interposedly contour the bit recess between the pinned layer and the sense layer. The barrier layer may comprise Aluminum Oxide. Moreover, the barrier layer and the magnetic sense layer may be planarized using a chemical-mechanical polishing technique so as to define a magnetic bit shape and stopping adjacent to the dielectric layer. The bit recess may comprise a recessed well that defines the magnetic bit shape, and the magnetic bit shape is elliptical and the recessed well has sloped interior walls.
In another embodiment, the aforementioned needs may be satisfied by an array of magnetic memory cells comprising a substrate, a first plurality of electrode traces formed in rows adjacent to the substrate, a plurality of pinned layers formed on the substrate so as to overlie the first plurality of electrode traces so as to be electrically coupled therewith, wherein each of the pinned layers provide a first magnetic component in a first direction, and a contiguous insulation layer formed in an overlying manner adjacent to the pinned layers and the substrate, wherein the contiguous insulation layer is formed so as to define an array of recessed wells. Additionally, the array of magnetic memory cells may further comprise an array of discrete soft layers overlying the array of recessed wells, wherein regions of the discrete soft layers produce a second magnetic component either in the first direction or in a second direction that is different from the first direction, and a second plurality of electrode traces formed in rows so as to overlie the array of discrete soft layers and be electrically coupled therewith, wherein conduction of voltage between the first and the second electrode results in a change in the direction of the magnetic component of the discrete soft layers thereby resulting in a detectable change in the resistance of the magnetic memory cells.
In still another embodiment, the aforementioned needs may be satisfied by a memory device formed adjacent to a substrate, wherein the memory device may comprise a lower electrode formed within the substrate, a dielectric layer formed adjacent to the substrate so as to define a recess above the lower electrode, a magnetic memory cell formed within the recess so as to contour the recess and electrically couple with the lower electrode, and an upper electrode formed above the magnetic memory cell and electrically coupled therewith. In one aspect, the lower electrode may be formed using a damascene process. The recess may comprise sloped interior walls and/or an elliptical recess with sloped interior side walls. The device may further comprise a thin dielectric layer having a via hole interposed between the magnetic memory cell and the upper electrode. Moreover, the magnetic memory cell may comprise an MRAM, wherein the magnetic memory cell comprises a lower magnetic sense layer, a barrier layer, an upper magnetic pinned layer, and a CMP stop layer.
In yet another embodiment, the aforementioned needs may be satisfied may an MRAM array comprising a plurality of lower electrode traces formed in rows adjacent to a substrate and a contiguous dielectric layer formed adjacent to the substrate so as to define an array of recessed wells with sloped interior walls above the plurality of lower electrode traces. In addition, the MRAM array may further comprise a plurality of MRAM cells formed within the array of recessed wells so as to contour the recess and electrically couple with the lower electrode and a plurality of upper electrodes formed above the plurality of MRAM cells and electrically coupled therewith.
Moreover, the aforementioned needs may be satisfied by a method of fabricating a magnetic memory device having a magnetic stack structure interposed between a lower and upper electrode. In one embodiment, the method may comprise forming an insulating layer so as to define a recessed well above the lower electrode traces, forming the magnetic stack structure within the recessed wells above the lower electrode, planarizing the magnetic stack structure to define a magnetic bit shape using chemical-mechanical polishing, and forming the second electrode on the magnetic stack structure.
In another embodiment, a method of fabricating a magnetic memory device may be utilized, wherein the method may comprise forming a first electrode having an upper exposed surface within a substrate using a damascene process, forming a magnetic pinned layer on the upper exposed surface of the first electrode so as to establish a conductive interconnection therewith, forming a dielectric layer adjacent to the substrate so as to provide a recessed region with sloped interior side walls adjacent to the magnetic pinned layer for the subsequent forming of an overlying barrier layer and a magnetic sense layer. The method may further comprise depositing the barrier layer overlying the magnetic pinned layer, depositing the magnetic sense layer overlying the barrier layer, planarizing the barrier layer and the magnetic sense layer so as to define at least one magnetic bit shape using a chemical-mechanical polishing technique and stopping adjacent to the dielectric layer, and forming the second electrode on the magnetic sense layer so as to establish a conductive interconnection therewith.
In still another embodiment, a method of fabricating a magnetic memory device on a substrate may comprise forming a lower electrode having an upper exposed surface within the substrate using a damascene process, forming a thick dielectric layer adjacent to the substrate so as to provide a recessed region above the upper exposed surface of the lower electrode, forming a magnetic pinned layer on the thick dielectric layer so as to overlie the recessed region, and forming a barrier layer that overlies the magnetic pinned layer. Additionally, the method may further comprise forming a magnetic sense layer that overlies the barrier layer, forming a CMP stop layer that overlies the magnetic sense layer, and planarizing the magnetic pinned layer, the barrier layer, the magnetic sense layer, and the CMP stop layer to define at least one magnetic bit shape using a chemical-mechanical polishing technique and stopping adjacent to the thick dielectric layer. Moreover, the method may comprise forming a thin dielectric layer adjacent to the thick dielectric layer and the CMP stop layer, forming at least one via hole in the thin dielectric layer so as to provide an opening adjacent to the CMP stop layer, and forming an upper electrode on the thin dielectric layer adjacent to the via holes so as to provide conductive contact to the CMP stop layer.
These and other objects and advantages of the present invention will become more fully apparent from the following description taken in conjunction with the accompanying drawings.